1. Field of the Invention
The present invention relates generally to the transfer of data between memory and various components in a computer system. More particularly, this invention relates to a system for expediting transactions between computer components and dynamic random access memory (DRAM). Still more particularly, the present invention relates to a memory control unit (MCU) which includes an edge generator for defining the timing of control signals during DRAM transactions and for minimizing any necessary delay required in the control signal timing.
2. Description of the Relevant Art
FIG. 1 is a block diagram of a prior art computer system 10 that comprises a microprocessor or central processing unit ("CPU") 12, a CPU local bus 14 coupled to the CPU 12 and to a memory controller 16, and a local bus peripheral device 18 also coupled to the CPU local bus 14. A system memory 17 also is shown coupled to the memory controller 16 through a memory bus 15. In addition, a PCI standard bus 20 couples to the CPU local bus 14 through a PCI bus bridge 22. A PCI peripheral device 28 is shown coupled to the PCI bus 20. The PCI peripheral device 28 may comprise a PCI Master controller that is capable of asserting ownership of the PCI bus during PCI Master cycles.
The microprocessor 12 shown in FIG. 1 may comprise a model 80486 microprocessor, and the CPU local bus 14 could comprise an 80486-style local bus. The CPU local bus 14 includes a set of data lines D[31:0], a set of address lines A[31:0], and a set of control lines (not specifically shown). Details regarding the various bus cycles and protocols of the 80486 CPU local bus 14 are not discussed in detail herein, as they are well known by those in the art, and are available in numerous publications. CPU 12, memory controller 16 and PCI bus bridge 22 have traditionally been fabricated on separate integrated circuit chips. A recent trend in computer systems has developed, however, in which the CPU core is combined with a variety of peripheral devices on a single integrated processor chip. An exemplary integrated processor chip includes a bus bridge that provides a high performance interface between an internal CPU local bus and an external PCI bus. By providing a high performance interface to an external PCI bus, relatively high performance characteristics can be achieved with respect to external data transfers.
The PCI bus bridge 22 provides a standard interface between the CPU local bus 14 and the PCI bus 20. As such, the PCI bus bridge 32 orchestrates the transfer of data, address, and control signals between the two buses. PCI bus 20 typically comprises a high performance peripheral bus that includes multiplexed data/address lines, and which supports burst-mode data transfers.
The burst mode feature allows reads or writes to consecutive memory locations at high speed, via burst cycles on the PCI bus. The normal procedure for reading or writing from memory is that the CPU in a first clock cycle generates the address signals on the address bus, and then in the following clock cycle, data is transferred to or from system memory 17. Since the data bus is 32-bits wide, a total of four 8-bit bytes of data can be read or written by the CPU for every two clock cycles. Each set of four 8-bit bytes transferred on the data bus is referred to as a "double word." In burst mode or page mode cycles, additional sequential double words may be transferred during subsequent clock cycles without intervening address phases. For example, a total of four double words can be read into the CPU using only five clock cycles because only the starting address is sent out on the address bus, and subsequently the first double word of data is read during the second cycle, the next double word of data during the third cycle, and so on. Burst mode operation thereby accommodates relatively high data transfer rates.
As noted, the PCI peripheral device 28 may comprise a PCI Master controller. In accordance with conventional techniques, the PCI Master may request "ownership" of the PCI bus, so that it can control transactions on the PCI bus 20. As one skilled in the art will understand, a plurality of PCI Masters may be included in the computer system, any of which may request ownership of the PCI bus 20. The PCI Master submits its request for ownership of the PCI bus 20 to the PCI bridge 22 on a control line in the PCI bus 20. The PCI bus bridge 22 typically arbitrates ownership requests among the various PCI Masters, and among the internal masters such as the CPU 12, and other internal masters. Typically, a priority ranking is assigned to each of the various Masters to assist the bus bridge 22 in its priority determination.
The system memory typically includes banks of dynamic random access memory (DRAM) circuits. The DRAM connects to the MCU via a memory bus, comprised of memory address lines, memory data lines, and various control lines. The DRAM banks, according to normal convention, comprises the working memory of the integrated processor. Data generally is transferred between DRAM 17 and other components in a computer system in two steps. First, the accessing component generates signals on the address bus representing the row address of the desired memory location, which are latched into the DRAM when the row address strobe (RAS) signal is asserted low. At the next, or at subsequent, clock cycles, the memory device latches in the column address signal when the column address strobe (CAS) is asserted low. During an early write transaction, data is written into memory on the falling edge of the CAS signal while WE is active. In a read cycle, data from the selected memory cell is driven onto the data output line shortly after the assertion of the CAS signal while WE is inactive.
The speed of memory circuits is based upon two timing parameters. The first parameter is memory access time, which is the minimum time required by the memory circuit to set up a memory address and produce or capture data on or from the data bus. The second parameter is the memory cycle time, which is the minimum time required between two consecutive accesses to the memory circuit. For DRAM circuits, the cycle time typically is approximately twice the access time. DRAM circuits generally have an access time in the approximate range of 60-100 nanoseconds, with cycle times of 120-200 nanoseconds. The extra time required for consecutive memory accesses in a DRAM circuit is necessary because the internal memory circuits require additional time to recharge (or "precharge") to accurately produce data signals. Thus, a microprocessor running at 10 Mhz cannot execute two memory accesses, in immediate succession (or in adjacent clock pulses), to the same 100 nanosecond DRAM chip, despite the fact that a clock pulse in such a microprocessor is generated every 100 nanoseconds. DRAM chips require time to stabilize before the next address in that chip can be accessed. Consequently, in such a situation the microprocessor must execute one or more loop cycles or wait states before it can again access data in the DRAM circuit. Typically, a memory controller unit ("MCU") is provided as part of the computer system to regulate accesses to the DRAM main memory.
Because of these limitations, memory constructed with DRAM circuits is not always capable of responding to memory accesses within the time interval allotted by the CPU. In this event, external circuitry must signal to the CPU that supplementary processor cycles, or wait states, are necessary before the data is ready on the data bus, or before data from the data bus has been stored by the memory circuits. In addition to slowing the processing of the CPU, wait states generally require use of the CPU local bus, thereby limiting access to the bus by other system circuitry.
The critical timing parameters of memory transactions is shown in FIGS. 3A and 3B. As shown generally in FIGS. 3A (read cycle) and 3B (early write cycle), the row address is driven on the address inputs of the DRAM memory when the RAS (row address strobe) control line is asserted (i.e. RAS is driven low). This clocks the row address into an internal row address latch. The row address must be stable for a period (t.sub.ASR) before RAS is asserted, and for a period (t.sub.RAH) after RAS is asserted. A typical time for t.sub.RAH is 15 nanoseconds. The address inputs then are changed to the column address, and CAS (column address strobe) is asserted (CAS is driven low). The column address set-up time (t.sub.ASC) is the minimum period by which the data on the column address must precede the assertion of CAS. The column address must remain stable for a period (t.sub.CAC) after RAS is asserted. A typical time period for t.sub.CAC is 35 nanoseconds. The CAS signal also functions as the output enable, so that whenever CAS is asserted, the three-state driver on the data pin out is enabled. The time when CAS can be asserted is determined by the minimum RAS-to-CAS delay period (t.sub.RCD).
The data is available after the access times from RAS (which is denoted as t.sub.RAC) and CAS (which is denoted as t.sub.CAC) have both been met. The limit of performance is determined by the access time from RAS (t.sub.RAC). Another timing parameter that is critical to memory accesses is the RAS precharge time (t.sub.RP). The precharge time (t.sub.RP) is the time required for the DRAM circuit to recover from the previous access. Another cycle cannot be started the instant that data is available. Thus, the cycle time for dynamic memories is greater than the access time. The difference between the access time and the cycle time is the precharge time. These timing characteristics of DRAM circuits become critical as one attempts to expedite memory transactions.
Each of the various steps in the memory transaction (i.e. driving the row address, the assertion of RAS, driving the column address, and the assertion of CAS) require minimum time periods as defined by FIGS. 3A and 3B. When configuring the system, the designer or user must determine when the control signals (such as RAS and CAS) will be asserted during a memory transaction and when the address signal will be switched from the row address to the column address. Typically, in prior art devices, some or all of the signals defining the memory transaction are synchronized with the system clock. Thus, as an illustration, RAS may be asserted at the rising edge of the system clock, the row address would be switched to the column address on the following rising clock edge, and CAS may be asserted at the subsequent rising edge of the system clock.
One apparent problem with this timing and synchronization of the memory control signals with the system clock is that if the memory control unit is unable to generate or assert the signals at the next rising edge of the system clock, then the memory control unit must wait until the next rising clock edge to assert the signal. Thus, for example in a local bus operating at 33 MHz (defining a clock period of 30 nanoseconds), if the MCU is incapable of asserting the CAS strobe signal on the clock rising edge following the selection of the column address, then the MCU would be required to wait until the next rising clock edge, which would not occur until 30 nanoseconds later. Waiting another 30 nanoseconds in a DRAM circuit with access times of 60 nanoseconds represents a large percentage of the access time that has been lost because of the inability to generate the CAS signal prior to the next rising edge of the system clock.
Another problem which further complicates the configuration of the timing parameters in a DRAM transaction is that in prior art designs, the timing of the control signals is predetermined during the design of the MCU. Unfortunately, this determination often is made before the designer knows what the actual propagation delay will be for the MCU logic and the integrated processor. If the designer subsequently learns that enough time has not been allotted to complete the critical timing requirements of a DRAM memory transaction, the timing may need to be reconfigured, which may mean accepting a large amount of delay (i.e., another clock cycle) to accommodate the critical timing parameters of the DRAM.
To date, none of the prior art MCU and.backslash.or integrated processor designs have provided a solution to these problems. As the operating speed of processors increases and as new generations of processors evolve, it will be advantageous to minimize the wait states and delays, such as those caused by the critical timing parameters of the DRAM, to fully exploit the capabilities of these new processors.